High performance Schottky barrier FET's and bipolar transistors have active regions in the bulk of a semiconductor body thus avoiding the deleterious effects of surface discontinuities on carrier mobilities. On the other hand, to make possible large scale integration, it is necessary to bring the active bulk regions of the device in contact with the top surface of the structure. In doing this, parasitic resistive and capacitive elements are created which degrade the high performance of the bulk device. Compromises between resistive and capacitive parasitics are difficult to achieve since decreasing or increasing the doping to minimize one of them, respectively, adversely impacts the other. Moreover, doping levels are generally determined by the design of bulk devices.
The performance obtained from conventionally fabricated Schottky barrier FET's is limited by:
(1) High source-gate and drain-gate parasitic resistance,
(2) High interelectrode capacitance, and
(3) Low interelectrode breakdown voltage.
For bipolar transistors the problems include:
(1) High extrinsic base resistance,
(2) Low base-emitter breakdown voltage,
(3) High base-emitter sidewall capacitance and
(4) Self-biasing along the emitter width, a deleterious effect known as emitter crowding.